انجمن کامپیوتر ایران

Two new high-performance Full Adders, purely designed with 3-input Majority-not function, are proposed in this paper. The Majority-not function is implemented efficiently by using only capacitors and a static CMOS inverter. This kind of design improves the parameters of the Full Adder cell and leads to high performance, driving capability, a high degree of regularity and simplicity. Five state-of-the-art 1-bit Full Adder cells and the proposed Full Adders are simulated using 0.18μm CMOS technology at three supply voltages. Simulation results demonstrate significant improvement in terms of power consumption and Power-Delay Product (PDP).