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Thermal Management of FPGA-based Embedded Systems at Operating System Level |
Tayyebeh Hashamdar
Hamid Noori
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سمپوزیوم سیستمها و فنآوریهای بیدرنگ و نهفته RTEST 2015 |
Field Programmable Gate Arrays (FPGAs) are well-knownplatforms for implementing embedded systems due toconfigurability. Recently, high temperature of FPGAs is becominga serious issue due to their higher logic density, clock frequency,and ... more
Field Programmable Gate Arrays (FPGAs) are well-knownplatforms for implementing embedded systems due toconfigurability. Recently, high temperature of FPGAs is becominga serious issue due to their higher logic density, clock frequency,and complexity. In this work we propose, implement, andevaluate an embedded system with a thermal aware operatingsystem on the virtex-5 FPGA. It measures the temperature of thedevice using the system monitor IP core configured in the operatingsystem and manages the temperature, not to violate threshold,using the task suspension feature of the operating system. Aresident task in the operating system regularly checks the temperatureof the device and does thermal management if neededby suspending other active tasks for a specified time slot. If thistime slot is correctly chosen, the method degrades performanceonly 7 percent while the temperature threshold is not violated. less
Field Programmable Gate Arrays (FPGAs) are well-knownplatforms for implementing embedded systems due toconfigurability. Recently, high temperature of FPGAs is becominga serious issue due to their higher logic density, clock frequency,and ... more |
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Two Effective Anomaly Correction Methods in Embedded Systems |
Roghayeh Mojarad
Hamid R. Zarandi
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سمپوزیوم سیستمها و فنآوریهای بیدرنگ و نهفته RTEST 2015 |
In this paper, two anomaly correction methods are proposed which are based on Markov and Stide detection methods. Both methods consist of three steps: 1) Training, 2) Anomaly detection and ... more
In this paper, two anomaly correction methods are proposed which are based on Markov and Stide detection methods. Both methods consist of three steps: 1) Training, 2) Anomaly detection and 3) Anomaly Correction. In training step, the Morkov-based method constructs a transition matrix; Stide-based method makes a database by events with their frequency. In detection step, when the probability of transition from previous event to current event does not reach a predefined threshold, the morkov-based method detects an anomaly. While, if frequency of unmatched events exceeds from the threshold value, Stide-based method determined an anomaly. In the correction step, the methods check the defined constraints for each anomalous event to find source of anomaly and a suitable way to correct the anomalous event. Evaluation of the proposed methods are done using a total of 7000 data sets. The window size of corrector and the number of injected anomalies varied between 3 and 5, 1 and 7, respectively. The experiments have been done to measure the correction coverage rate for Markov-based and Stide-based methods which are on average 77.66% and 60.9%, respectively. Area consumptions in Makov-based and Stide-based methods are on average 415.48µm2and 239.61 µm2, respectively. less
In this paper, two anomaly correction methods are proposed which are based on Markov and Stide detection methods. Both methods consist of three steps: 1) Training, 2) Anomaly detection and ... more |
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A memory-centric approach to enable timing-predictability within embedded many-core accelerators |
Paolo Burgio
Andrea Marongiu
Paolo Valente
Marko Bertogna
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سمپوزیوم سیستمها و فنآوریهای بیدرنگ و نهفته RTEST 2015 |
There is an increasing interest among real-time systemsarchitects for multi- and many-core accelerated platforms. Themain obstacle towards the adoption of such devices withinindustrial settings is related to the difficulties in ... more
There is an increasing interest among real-time systemsarchitects for multi- and many-core accelerated platforms. Themain obstacle towards the adoption of such devices withinindustrial settings is related to the difficulties in tightly estimatingthe multiple interferences that may arise among the parallelcomponents of the system. This in particular concerns concurrentaccesses to shared memory and communication resources. Existingworst-case execution time analyses are extremely pessimistic,especially when adopted for systems composed of hundreds-to-thousandsof cores. This significantly limits the potential forthe adoption of these platforms in real-time systems. In thispaper, we study how the predictable execution model (PREM), amemory-aware approach to enable timing-predictability in real-timesystems, can be successfully adopted on multi- and many-coreheterogeneous platforms. Using a state-of-the-art multi-coreplatform as a testbed, we validate that it is possible to obtain anorder-of-magnitude improvement in the WCET bounds of parallelapplications, if data movements are adequately orchestrated inaccordance with PREM. We identify which system parametersmostly affect the tremendous performance opportunities offeredby this approach, both on average and in the worst case, movingthe first step towards predictable many-core systems. less
There is an increasing interest among real-time systemsarchitects for multi- and many-core accelerated platforms. Themain obstacle towards the adoption of such devices withinindustrial settings is related to the difficulties in ... more |
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Response-Time Minimization in Soft Real-Time Systems with Temperature-Affected Reliability Constraint |
Ahad Mozafari Fard
Mehdi Ghasemi
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سمپوزیوم سیستمها و فنآوریهای بیدرنگ و نهفته RTEST 2015 |
With the continuous shrinking of technology size, chip temperature, and consequently the temperature-affected error vulnerability have been increased. To control these issues, some temperature and reliability constraints have been added, ... more
With the continuous shrinking of technology size, chip temperature, and consequently the temperature-affected error vulnerability have been increased. To control these issues, some temperature and reliability constraints have been added, which has led to confined performance. This paper proposes a proactive approach using thermal throttling to guarantee the failure rate of running tasks while minimizing the corresponding response-times. The task’s jobs are executed according to the as soon as possible (ASAP) policy and the temperature of the processor is controlled based on the vulnerability factor of the running task. The optimality of the method in the case of first-come first-served (FCFS) task scheduling policy has also been proven. Simulation results reveal that the proposed method can reduce the job miss ratio and response-times, respectively, for at least 17% and 16% on the average. less
With the continuous shrinking of technology size, chip temperature, and consequently the temperature-affected error vulnerability have been increased. To control these issues, some temperature and reliability constraints have been added, ... more |
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A Predictable Interrupt Management Policy for Real-Time Operating Systems |
Javad Ebrahimian Amiri
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سمپوزیوم سیستمها و فنآوریهای بیدرنگ و نهفته RTEST 2015 |
Real-time operating systems play important roles indeveloping many of today’s embedded systems. Majority of theseembedded systems have intense interactions with the environmentthrough I/O devices, namely sensors and actuators. Interruptsare often ... more
Real-time operating systems play important roles indeveloping many of today’s embedded systems. Majority of theseembedded systems have intense interactions with the environmentthrough I/O devices, namely sensors and actuators. Interruptsare often used by the operating systems to handle these interactionsthrough executing the corresponding interrupt serviceroutines (ISRs). ISRs are usually executed non-preemptively atsome priorities higher than system tasks. Depending on theinterrupt frequency, this prioritization can result in problemslike unresponsiveness and unpredictability in the system, even forthe high priority tasks. This incurs a type of priority inversionwhich we call it ISR-task priority inversion (ITPI). This paperuses threaded interrupts and employs the priority inheritanceprotocol (PIP) to enforce each interrupt service thread (IST) tobe executed at its owner’s priority, causing less interference withhigher priority tasks. Two PIP-based approaches are proposedand implemented: 1) Static priority linked list, which uses PIPonly when a task starts; experimental results show that thisapproach can tolerate some simple forms of ITPI, and 2) Dynamicpriority bitmap, which employs PIP whenever a task needs anIST; experiments show that more complex forms of ITPI can betolerated with this approach. The almost extensive experimentalresults show that using the dynamic priority approach enhancesthe real-time system predictability compared to the commonapproaches. less
Real-time operating systems play important roles indeveloping many of today’s embedded systems. Majority of theseembedded systems have intense interactions with the environmentthrough I/O devices, namely sensors and actuators. Interruptsare often ... more |
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HDL Based Simulation Framework for a DPA Secured Embedded System |
Danial Kamran
Ali Marjovi
Ali Fanian
Mehran Safayani
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سمپوزیوم سیستمها و فنآوریهای بیدرنگ و نهفته RTEST 2015 |
Side Channel Analysis (SCA) are still harmfulthreats against security of embedded systems. Due to the fact thatevery kind of SCA attack or countermeasure against it needs to beimplemented before evaluation, ... more
Side Channel Analysis (SCA) are still harmfulthreats against security of embedded systems. Due to the fact thatevery kind of SCA attack or countermeasure against it needs to beimplemented before evaluation, a huge amount of time and costof this process is paid for providing high resolution measurementtools, calibrating them and also implementation of proposeddesign on ASIC or target platform. In this paper, we haveintroduced a novel simulation platform for evaluation of powerbased SCA attacks and countermeasures. We have used Synopsyspower analysis tools in order to simulate a processor and implementa successful Differential Power Analysis (DPA) attack on it.Then we focused on the simulation of a common countermeasureagainst DPA attacks called Random Delay Insertion (RDI). Wesimulated a resistant processor that uses this policy. In the nextstep we showed how the proposed framework can help to extractpower characteristics of the simulated processor and implementpower analysis based reverse engineering on it. We used thisapproach in order to detect DPA related assembly instructionsbeing executed on the processor and performed a DPA attack onthe RDI secured processor. Experiments were carried out on aPico-blaze simulated processor. less
Side Channel Analysis (SCA) are still harmfulthreats against security of embedded systems. Due to the fact thatevery kind of SCA attack or countermeasure against it needs to beimplemented before evaluation, ... more |
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A Partial Task Replication Algorithm for Fault-Tolerant FPGA-based Soft-Multiprocessors |
Masoume Zabihi
Hamed Farbeh
Seyed Ghassem Miremadi
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سمپوزیوم سیستمها و فنآوریهای بیدرنگ و نهفته RTEST 2015 |
FPGA-based multiprocessors, referred as soft-multiprocessors, have an increasing use in embedded systems due to appealing SRAM features. More than 95% of such FPGAs are occupied by SRAM cells constructing the ... more
FPGA-based multiprocessors, referred as soft-multiprocessors, have an increasing use in embedded systems due to appealing SRAM features. More than 95% of such FPGAs are occupied by SRAM cells constructing the configuration bits. These SRAM cells are highly vulnerable to soft errors threatening the reliability of the system. This paper proposes a fault-tolerant method to detect and correct errors in the configuration bits. The main of this method is to analyze the scheduled task graph and select a subset of tasks to be replicated in multiple processors based on the utilization of the processors in different execution phases. To this end, 1) errors are detected by re-executing a subset of tasks in multiple processors and comparing their output; 2) errors are corrected by re-downloading the fault-free bitstream; 3) errors are recovered from correct checkpoints. To evaluate the proposed method, a FPGA containing four and eight processors running randomly generated task graphs is evaluated. The simulation results show that the performance overhead of the proposed method for four and eight processors is 20% and 15%, respectively. These values for lockstep method are about 90% and 45%, respectively. Moreover, the area overhead of the proposed method is zero. less
FPGA-based multiprocessors, referred as soft-multiprocessors, have an increasing use in embedded systems due to appealing SRAM features. More than 95% of such FPGAs are occupied by SRAM cells constructing the ... more |
خرید مقاله
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Fault-Tolerant Architecture and CAD Algorithm for Field-Programmable Pin-Constrained Digital Microfluidic Biochips |
Alireza Abdoli
Ali Jahanian
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سمپوزیوم سیستمها و فنآوریهای بیدرنگ و نهفته RTEST 2015 |
Advent of digital microfluidic embedded biochips has revolutionized accomplishment of laboratory procedures. Digital microfluidic biochips provide general-purpose assay execution along with several advantages compared with traditional benchtop chemistry procedures; advantages ... more
Advent of digital microfluidic embedded biochips has revolutionized accomplishment of laboratory procedures. Digital microfluidic biochips provide general-purpose assay execution along with several advantages compared with traditional benchtop chemistry procedures; advantages of these modern devices encompass automation, miniaturization and lower costs. However these embedded systems are vulnerable to various types of faults which can adversely affect the integrity of assay execution outcome. This paper addresses fault tolerance of field-programmable pin-constrained digital microfluidic biochips from various aspects; evaluating effects of faulty mix modules, faulty Storage / Split / Detection (SSD) modules and faulty regions within routing paths. The simulation results show that in case of faulty mixing modules the operation times were retained however the 5 % advantage in routing times contributes to 1 % improvement of total bioassay execution time; considering overheads incurred by faulty mixing modules, the results show no overhead in operation times and 20 % overhead in routing times which in turn incur 2 % overhead on total bioassay execution time. In case of faulty SSD modules the operation time remains the same however as a result of 19 % advantage in routing times the total bioassay execution time shows 2 % improvement; regarding the overheads incurred by faulty SSD modules it is observed that despite the 4 % over-head in routing times there is no overhead with the total bioassay execution time. less
Advent of digital microfluidic embedded biochips has revolutionized accomplishment of laboratory procedures. Digital microfluidic biochips provide general-purpose assay execution along with several advantages compared with traditional benchtop chemistry procedures; advantages ... more |
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A2CM2: Aging-Aware Cache Memory Management Technique |
Reza Nazari
Nezam Rohbani
Hamed Farbeh
Zahra Shirmohammadi
Seyed Ghassem Miremadi
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سمپوزیوم سیستمها و فنآوریهای بیدرنگ و نهفته RTEST 2015 |
Negative Bias Temperature Instability (NBTI) in CMOS devices is known as the major source of aging effect which is leading to performance and reliability degradation in modern processors. Instruction-cache (I-cache), ... more
Negative Bias Temperature Instability (NBTI) in CMOS devices is known as the major source of aging effect which is leading to performance and reliability degradation in modern processors. Instruction-cache (I-cache), which has a decisive role in performance and reliability of the processor, is one of the most prone modules to NBTI. Variations in duty cycle and long-time residency of data blocks in I-cache lines (stress condition) are the two major causes of NBTI acceleration. This paper proposes a novel I-cache management technique to minimize the aging effect in the I-cache SRAM cells. The proposed technique consists of a smart controller that monitors the cache lines behavior and distributes uniformly stress condition for each line. The simulation results show that the proposed technique reduces the NBTI effect in I-cache significantly as compared to normal operation. Moreover, the energy consumption and the performance overheads of the proposed technique are negligible. less
Negative Bias Temperature Instability (NBTI) in CMOS devices is known as the major source of aging effect which is leading to performance and reliability degradation in modern processors. Instruction-cache (I-cache), ... more |
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Offline Replication and Online Energy Management for Hard Real-Time Multicore Systems |
Farimah R. Poursafaei
Sepideh Safari
Mohsen Ansari
Mohammad Salehi
Alireza Ejlali
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سمپوزیوم سیستمها و فنآوریهای بیدرنگ و نهفته RTEST 2015 |
For real-time embedded systems, energy consumption and reliability are two major design concerns. We consider the problem of minimizing the energy consumption of a set of periodic real-time applications when ... more
For real-time embedded systems, energy consumption and reliability are two major design concerns. We consider the problem of minimizing the energy consumption of a set of periodic real-time applications when running on a multi-core system while satisfying given reliability targets. Multi-core platforms provide a good capability for task replication in order to achieve given reliability targets. However, careless task replication may lead to significant energy overhead. Therefore, to provide a given reliability level with a reduced energy overhead, the level of replication and also the voltage and frequency assigned to each task should be determined cautiously. The goal of this paper is to find the level of replication, voltage and frequency assignment, and core allocation for each task at design time, in order to achieve a given reliability level while minimizing the energy consumption. Also, at run-time, we find the tasks that have finished correctly and cancel the execution of their replicas to achieve even more energy saving. We evaluated the effectiveness of our scheme through extensive simulations. The results show that our scheme provides up to 50% (in average by 47%) energy saving while satisfying a broad range of reliability targets. less
For real-time embedded systems, energy consumption and reliability are two major design concerns. We consider the problem of minimizing the energy consumption of a set of periodic real-time applications when ... more |
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