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Paper Title |
Authors |
Conference |
Abstract |
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Multi Parametric Optimized Architectural Synthesis of an Application Specific Processor |
Summit Sehgal
Reza Sedaghat
Anirban Sengupta
Zhipeng Zeng
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چهاردهمین کنفرانس بین‌المللی سالانه انجمن کامپیوتر ایران |
Recent advancements in the field of multimedia
and wireless communications have led to a wide array of
application and services requiring high data processing rate
at minimal power consumption. This new generation of ... more
Recent advancements in the field of multimedia
and wireless communications have led to a wide array of
application and services requiring high data processing rate
at minimal power consumption. This new generation of data
hungry portable devices requires power efficient hardware
solutions where the operational specifications are as
important as objective functionality. Conventional
processing solutions like MIPS fall short on real time
computational intensive operations due to large software
overhead. This class of applications demands dedicated
hardware units like Application Specific Processors (ASP)
working as hardware accelerators for intensive data
processing operations. In this paper we describe a novel
Register Transfer Level (RTL) synthesis process of a power
and throughput optimized ASP for a sample application.
The ASP implemented on an FPGA, can serve as a
hardware accelerator for system on chip (SOC) or as a
standalone Application Specific Integrated Circuit (ASIC)
at silicon level. less
Recent advancements in the field of multimedia
and wireless communications have led to a wide array of
application and services requiring high data processing rate
at minimal power consumption. This new generation of ... more |
خرید مقاله
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A Flexible Design of Network on Chip Router based on Handshaking Communication Mechanism |
Seyyed Amir Asghari
Hossein Pedram
Mohammad Khademi
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چهاردهمین کنفرانس بین‌المللی سالانه انجمن کامپیوتر ایران |
One of the important issues in power and
performance trade off analysis in Network on Chip
designs is communication. Communication portion in
the power consumption of System on Chip can be up to
50% ... more
One of the important issues in power and
performance trade off analysis in Network on Chip
designs is communication. Communication portion in
the power consumption of System on Chip can be up to
50% of the whole power of consumption of the chip.
This deems to be more important for Network on Chips
which center around an intercommunication networks.
Many Networks on Chip routers have been designed;
however most of them have not been implemented until
now. In this paper, design and implementation of a
synchronous Network on Chip router based on
asynchronous communication mechanism are
presented. We designed a router with scalability
feature which is synthesized in both FPGA and ASIC
infrastructures. In addition, the proposed router uses
low resource utilization percentage of FPGA and
ASIC. less
One of the important issues in power and
performance trade off analysis in Network on Chip
designs is communication. Communication portion in
the power consumption of System on Chip can be up to
50% ... more |
خرید مقاله
|
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New high-performance majority function based Full Adders |
Mohammad Hossein Moaiyeri
Reza Faghih Mirzaee
Keivan Navi
Tooraj Nikoubin
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چهاردهمین کنفرانس بین‌المللی سالانه انجمن کامپیوتر ایران |
Two new high-performance Full Adders, purely
designed with 3-input Majority-not function, are
proposed in this paper. The Majority-not function is
implemented efficiently by using only capacitors and
a static CMOS inverter. This kind of ... more
Two new high-performance Full Adders, purely
designed with 3-input Majority-not function, are
proposed in this paper. The Majority-not function is
implemented efficiently by using only capacitors and
a static CMOS inverter. This kind of design improves
the parameters of the Full Adder cell and leads to
high performance, driving capability, a high degree
of regularity and simplicity. Five state-of-the-art 1-bit
Full Adder cells and the proposed Full Adders are
simulated using 0.18μm CMOS technology at three
supply voltages. Simulation results demonstrate
significant improvement in terms of power
consumption and Power-Delay Product (PDP). less
Two new high-performance Full Adders, purely
designed with 3-input Majority-not function, are
proposed in this paper. The Majority-not function is
implemented efficiently by using only capacitors and
a static CMOS inverter. This kind of ... more |
خرید مقاله
|
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An Innovative Fault Injection Method in Embedded Systems via Background Debug Mode |
Seyyed Amir Asghari
Mohammad Khademi
Morteza Ansarinia
Hamid Reza Zarandi
Hossein Pedram
|
چهاردهمین کنفرانس بین‌المللی سالانه انجمن کامپیوتر ایران |
The embedded systems usage in different applications
is prevalent in recent years. These systems include a wide
range of equipments from cell phones to medical
instruments, which consist of hardware and software. In
many ... more
The embedded systems usage in different applications
is prevalent in recent years. These systems include a wide
range of equipments from cell phones to medical
instruments, which consist of hardware and software. In
many examples of embedded systems, fault occurrence can
lead to serious dangers in system behavior (for example in
satellites). Therefore, we try to increase the fault tolerance
feature in these systems. Therefore, we need some
mechanisms that increase the robustness and reliability of
such systems. These objects cause the on-line test to be a
great concern. It is not important that these mechanisms
work in which level (Hardware level, Software level or
Firmware). The major concern is that how well these
systems can provide debugging, test and verification
features for the user regardless of their implementation
levels. Background Debug Module is a real time tool for
these features. In this paper we apply an innovative way to
use the BDM tool for fault injection in an embedded
system. less
The embedded systems usage in different applications
is prevalent in recent years. These systems include a wide
range of equipments from cell phones to medical
instruments, which consist of hardware and software. In
many ... more |
خرید مقاله
|
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An Efficient Hardware Implementation for H.264 Binary Arithmetic Encoder |
Farzad Zargari
Ehsan Azimi
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چهاردهمین کنفرانس بین‌المللی سالانه انجمن کامپیوتر ایران |
Binary Arithmetic Coding (BAC) is among the
techniques used in H.264 video coding standard to
improve the coding efficiency. BAC includes an
iterative process of renormalization with up to seven
iterations for coding each ... more
Binary Arithmetic Coding (BAC) is among the
techniques used in H.264 video coding standard to
improve the coding efficiency. BAC includes an
iterative process of renormalization with up to seven
iterations for coding each symbol. Since BAC is also a
computational intensive unit in H.264 encoder, various
hardware realizations have been proposed for it in the
literature. In this paper, we propose a hardware
implementation for BAC, which uses lookup table to
avoid the iterative coding process and achieves coding
rate of one symbol per clock at 260 MHz clock rate.
Post synthesize simulation results indicate that the
proposed architecture is a resource and speed efficient
hardware for H.264 binary arithmetic encoder. less
Binary Arithmetic Coding (BAC) is among the
techniques used in H.264 video coding standard to
improve the coding efficiency. BAC includes an
iterative process of renormalization with up to seven
iterations for coding each ... more |
خرید مقاله
|
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Comparison of Dual Rail and an Enhanced Bundled Data Asynchronous Protocols Noise Robustness in the GALS NoC Link Application |
Soodeh Aghli Moghaddam
Siamak Mohammadi
Parviz Jabedar Maralani
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چهاردهمین کنفرانس بین‌المللی سالانه انجمن کامپیوتر ایران |
Asynchronous protocols exhibit various noise robustness
and when used in GALS NoC links, they can directly affect the
signal integrity. In this paper we study the noise robustness of
two well-known asynchronous protocols, ... more
Asynchronous protocols exhibit various noise robustness
and when used in GALS NoC links, they can directly affect the
signal integrity. In this paper we study the noise robustness of
two well-known asynchronous protocols, namely Dual-Rail
(DRP) and Bundled-Data (BDP) in the GALS NoC links, and
subsequently confirm our claims through simulations. We
apply an enhanced version of BDP and DRP to 32/64 parallel
line links, show results in terms of noise robustness using
global interconnect features, specified in the ITRS roadmap
for 32nm technology.
The simulation results for two thousand random generated
inputs show that the number and the amplitude of noise
glitches over ‘0’ state lines as well as the required threshold
voltage needed for avoiding errors in BDP link are much
lower than in DRP's. Therefore, BDP links can present better
signal integrity features and have less overhead compared to
DRP's, employing only some simple noise reduction
techniques and more timing adjustment effort. less
Asynchronous protocols exhibit various noise robustness
and when used in GALS NoC links, they can directly affect the
signal integrity. In this paper we study the noise robustness of
two well-known asynchronous protocols, ... more |
خرید مقاله
|
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A Novel Arbitration Scheme for Bandwidth and Jitter Guarantees in Asynchronous NoCs |
Marzieh Lenjani
Mahmoud Reza Hashemi
|
چهاردهمین کنفرانس بین‌المللی سالانه انجمن کامپیوتر ایران |
On-chip network interconnections or Network-on-
Chip (NOC) is viewed as a possible solution to global
wiring issues in highly integrated complex systems. In
current NoCs and in order to promote system level
integrity, there ... more
On-chip network interconnections or Network-on-
Chip (NOC) is viewed as a possible solution to global
wiring issues in highly integrated complex systems. In
current NoCs and in order to promote system level
integrity, there is a growing need to provide different
traffic classes, each with a different Quality-of-Service
guarantee. In synchronous NOCs guaranteed service is
provided by reserving time slots. Asynchronous NOC
implementation, on the other hand, eliminates the need
for synchronization when crossing clock domains. In
asynchronous NOCs there is no notation of time and
arbitration. Any delay in arbitration or refusing
requests in arbitration results in the accumulation of
data in switch buffers. In this paper a novel arbitration
scheme for clockless NOCs has been proposed that is
able to service a connection without any halt or jitter
in streaming. Consequently, links with a burst traffic
pattern and guaranteed bandwidth requirement can be
implemented without any large buffers. Simulation
results indicate that the proposed method is able to
reduce switch buffer size, and hence power
consumption in any NoC platform that is providing
guaranteed bandwidth requirements in applications
with burst data characteristics. For instance, in an
MPEG-2 decoder mapped to a 3x2 mesh with 8
guaranteed bandwidth channels in each port, the
proposed arbitration scheme is able to reduce the
buffer size by 25%. The improvement increases to %47
for a JPEG2000 encoder mapped to a 3x3 mesh. less
On-chip network interconnections or Network-on-
Chip (NOC) is viewed as a possible solution to global
wiring issues in highly integrated complex systems. In
current NoCs and in order to promote system level
integrity, there ... more |
خرید مقاله
|
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Power Comparison of an Asynchronous and Synchronous Network on Chip Router |
Pooria M.Yaghini
Ashkan Eghbal
S.A. Asghari
H. Pedram
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چهاردهمین کنفرانس بین‌المللی سالانه انجمن کامپیوتر ایران |
This paper presents an asynchronous and a
synchronous NoC router architecture. The
asynchronous scheme is implemented by the help of
CSP-Verilog language and the synchronous one is
designed employing VHDL language. Their designs
are similar ... more
This paper presents an asynchronous and a
synchronous NoC router architecture. The
asynchronous scheme is implemented by the help of
CSP-Verilog language and the synchronous one is
designed employing VHDL language. Their designs
are similar except the extra links which are in charge
of handshaking processes in asynchronous
architecture. According to the experimental results
the transition counts of buffer, and switch
components in synchronous router are almost 82%
and 60% of asynchronous one, respectively. On the
other hand, the transition counting of routing unit in
asynchronous NoC router is nearly 73% of
synchronous one. Power consumption of them are
evaluated according to the obtained transition
counting. Based on the comparison the power
consumption of buffer and switch components are
almost same due to their similar structure. However,
the power consumption of routing unit component in
asynchronous design is lower than synchronous one. less
This paper presents an asynchronous and a
synchronous NoC router architecture. The
asynchronous scheme is implemented by the help of
CSP-Verilog language and the synchronous one is
designed employing VHDL language. Their designs
are similar ... more |
خرید مقاله
|
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K-Anonymity Privacy Protection Using Ontology |
Maedeh Ashouri Talouki
Mohammad-ali NematBakhsh
Ahmad Baraani
|
چهاردهمین کنفرانس بین‌المللی سالانه انجمن کامپیوتر ایران |
Blinded data mining is a branch of data mining
technique which is focused on protecting user privacy.
To mine sensitive data such as medical information, it
is desirable to protect privacy and there ... more
Blinded data mining is a branch of data mining
technique which is focused on protecting user privacy.
To mine sensitive data such as medical information, it
is desirable to protect privacy and there is not worry
about revealing personalized data. In this paper a new
approach for blinded data mining is suggested. It is
based on ontology and k-anonymity generalization
method. Our method generalizes a private table by
considering table fields ontology, so that each tuple
will become k-anonymous and less specific to not
reveal sensitive information. This method is
implemented using protégé and java for evaluation. less
Blinded data mining is a branch of data mining
technique which is focused on protecting user privacy.
To mine sensitive data such as medical information, it
is desirable to protect privacy and there ... more |
خرید مقاله
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Adaptive and Cooperative Multi-Agent Fuzzy System Architecture |
Fatemeh Daneshfar
Fardin Akhlaghian
Fathollah Mansoori
|
چهاردهمین کنفرانس بین‌المللی سالانه انجمن کامپیوتر ایران |
The traffic congestion problem in urban areas is
worsening since traditional traffic signal control systems
cannot provide efficient traffic control. Therefore, dynamic
traffic signal control in Intelligent Transportation System
(ITS) recently has received increasing ... more
The traffic congestion problem in urban areas is
worsening since traditional traffic signal control systems
cannot provide efficient traffic control. Therefore, dynamic
traffic signal control in Intelligent Transportation System
(ITS) recently has received increasing attention. This study
devised an adaptive and cooperative multi-agent fuzzy system
for a decentralized traffic signal control. To achieve this goal
we have worked on a model, which has three levels of control.
Every intersection is controlled by its own traffic situation, its
neighboring intersections recommendations and a knowledge
base, which provides the traffic pattern of each intersection in
any particular day of the week and hour of the day. The
proposed architecture comprises a knowledge base, prediction
module and a traffic observer that provide data to real traffic
data preparation module, then a decision-making layer takes
decision to how long should the intersection green light be
extended. The proposed architecture can achieve dynamic
traffic signal control. We have also developed a NetLogobased
traffic simulator to serve as the agents’ world. Our
approach is tested with traffic control of a large connected
junction and the result obtained is promising; The average
delay time can be reduced by 21.76% compared to the
conventional fixed sequence traffic signal and 14.77%
compared to the vehicle actuated traffic signal control
strategy. less
The traffic congestion problem in urban areas is
worsening since traditional traffic signal control systems
cannot provide efficient traffic control. Therefore, dynamic
traffic signal control in Intelligent Transportation System
(ITS) recently has received increasing ... more |
خرید مقاله
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