مشاهده مشخصات مقاله
A System-Level Verification Methodology Using Performance and Functional Assertions
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نویسنده (ها) |
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Hassan Hatefi Ardakani
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Amir Masoud Gharehbaghi
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Shaahin Hessabi
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مربوط به کنفرانس |
دوازدهمین کنفرانس بینالمللی سالانه انجمن کامپیوتر ایران |
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چکیده |
As the designs get more complex, more sophisticated verification methodologies are required. At higher
levels of abstraction, design and verification methodologies are required to minimize the cost of electronic
product design. In this paper we integrate an assertion-based verification methodology with our objectoriented
system-level synthesis methodology. Functional and performance assertions, based on Property
Specification Language (PSL) and Logic of Constrains (LOC) are written during design process. Trace
checkers are automatically generated to validate particular simulation runs or to analyze their performance
characteristic(s). Following the case study, we demonstrate that the assertion-based verification is
highly useful for both functional and performance system-level verification. |
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قیمت |
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برای اعضای سایت : ۱٠٠,٠٠٠ ریال
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برای دانشجویان عضو انجمن : ۲٠,٠٠٠ ریال
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برای اعضای عادی انجمن : ۴٠,٠٠٠ ریال
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خرید مقاله
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